I often find Bash syntax very helpful, e.g. process substitution like in
diff <(sort file1) <(sort file2).
Is it possible to use such Bash commands in a Makefile? I'm thinking of something like this:
file-differences: diff <(sort file1) <(sort file2) > $@
In my GNU Make 3.80 this will give an error since it uses the
shell instead of
bash to execute the commands.
From the GNU Make documentation,
5.3.1 Choosing the Shell ------------------------ The program used as the shell is taken from the variable `SHELL'. If this variable is not set in your makefile, the program `/bin/sh' is used as the shell.
SHELL := /bin/bash at the top of your makefile, and you should be good to go.
BTW: You can also do this for one target, at least for GNU Make. Each target can have its own variable assignments, like this:
all: a b a: @echo "a is $$0" b: SHELL:=/bin/bash # HERE: this is setting the shell for b only b: @echo "b is $$0"
a is /bin/sh b is /bin/bash
See "Target-specific Variable Values" in the documentation for more details. That line can go anywhere in the Makefile, it doesn't have to be immediately before the target.
You can call
bash directly, use the
bash -c "diff <(sort file1) <(sort file2) > $@"
Of course, you may not be able to redirect to the variable $@, but when I tried to do this, I got
-bash: $@: ambiguous redirect as an error message, so you may want to look into that before you get too into this (though I'm using bash 3.2.something, so maybe yours works differently).